HD64F2149 Datasheet, PDF (182/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

16-Bit, 2-State Access Space: Figures 6.7 to 6.9 show the bus timing for 16-bit, 2-state access
space. When 16-bit access space is accessed, the upper data bus (D15 to D8) is used for even
addresses and the lower data bus (D7 to D0) for odd addresses.
Wait states cannot be inserted.
Bus cycle
T₁
T₂
ø
Address bus
AS/IOS (IOSE = 1)
AS/IOS (IOSE = 0)
RD
Read D15 to D8
Valid
D7 to D0
HWR
Write
LWR
D15 to D8
Invalid
High
Valid
D7 to D0
Undefined
Figure 6.7 16-Bit, 2-State Access Space Bus Timing (1)
(Even Address Byte Access)
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