HD64F2149 Datasheet, PDF (888/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

MRA—DTC Mode Register A
H'EC00–H'EFFF
DTC
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
SM1 SM0 DM1 DM0 MD1 MD0 DTS
Sz
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
—
—
—
—
—
—
—
—
DTC data transfer size
0 Byte-size transfer
1 Word-size transfer
DTC transfer mode select
0 Destination side is repeat
area or block area
1 Source side is repeat area
or block area
DTC mode
0 0 Normal mode
1 Repeat mode
1 0 Block transfer mode
1—
Destination address mode
0 — DAR is fixed
1 0 DAR is incremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
1 DAR is decremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
Source address mode
0 — SAR is fixed
1 0 SAR is incremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
1 SAR is decremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
854