HD64F2149 Datasheet, PDF (408/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 5—CSYNCI Edge (CEDG): Detects a rising edge on the CSYNCI pin.
Bit 5
CEDG
0
1
Description
[Clearing condition]
When 0 is written in CEDG after reading CEDG = 1
[Setting condition]
When a rising edge is detected on the CSYNCI pin
(Initial value)
Bit 4—HFBACKI Edge (HFEDG): Detects a rising edge on the HFBACKI pin.
Bit 4
HFEDG
0
1
Description
[Clearing condition]
When 0 is written in HFEDG after reading HFEDG = 1
[Setting condition]
When a rising edge is detected on the HFBACKI pin
(Initial value)
Bit 3—VFBACKI Edge (VFEDG): Detects a rising edge on the VFBACKI pin.
Bit 3
VFEDG
0
1
Description
[Clearing condition]
When 0 is written in VFEDG after reading VFEDG = 1
[Setting condition]
When a rising edge is detected on the VFBACKI pin
(Initial value)
Bit 2—Pre-Equalization Flag (PREQF): Detects the occurrence of an IHI signal 2fH
modification condition. The generation of a falling/rising edge in the IHI signal during a mask
interval is expressed as the occurrence of a 2fH modification condition. For details, see section
13.3.4, IHI Signal 2fH Modification.
Bit 2
PREQF
0
1
Description
[Clearing condition]
When 0 is written in PREQF after reading PREQF = 1
[Setting condition]
When an IHI signal 2fH modification condition is detected
(Initial value)
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