HD64F2149 Datasheet, PDF (29/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

18B.1.2 Block Diagram.................................................................................................. 574
18B.1.3 Pin Configuration ............................................................................................. 575
18B.1.4 Register Configuration ..................................................................................... 576
18B.2 Register Descriptions........................................................................................................ 577
18B.2.1 System Control Registers (SYSCR, SYSCR2) ................................................ 577
18B.2.2 Host Interface Control Registers 0 and 1 (HICR0, HICR1) ............................ 578
18B.2.3 Host Interface Control Registers 2 and 3 (HICR2, HICR3) ............................ 585
18B.2.4 LPC Channel 3 Address Register (LADR3) .................................................... 588
18B.2.5 Input Data Registers (IDR1, IDR2, IDR3)....................................................... 589
18B.2.6 Output Data Registers (ODR1, ODR2, ODR3)................................................ 590
18B.2.7 Two-Way Data Registers (TWR0 to TWR15)................................................. 591
18B.2.8 Status Registers (STR1, STR2, STR3)............................................................. 592
18B.2.9 SERIRQ Control Registers (SIRQCR0, SIRQCR1) ........................................ 595
18B.2.10 Module Stop Control Register (MSTPCR) ...................................................... 603
18B.3 Operation .......................................................................................................................... 604
18B.3.1 Host Interface Activation ................................................................................. 604
18B.3.2 LPC I/O Cycles ................................................................................................ 604
18B.3.3 A20 Gate .......................................................................................................... 606
18B.3.4 Host Interface Shutdown Function (LPCPD)................................................... 609
18B.3.5 Host Interface Serial Interrupt Operation (SERIRQ) ....................................... 612
18B.3.6 Host Interface Clock Start Request (CLKRUN) .............................................. 615
18B.4 Interrupt Sources .............................................................................................................. 616
18B.4.1 IBF1, IBF2, IBF3, ERRI .................................................................................. 616
18B.4.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, HIRQ12 .......................... 616
18B.5 Usage Notes...................................................................................................................... 618
Section 19 D/A Converter ................................................................................................. 621
19.1 Overview............................................................................................................................ 621
19.1.1 Features ................................................................................................................ 621
19.1.2 Block Diagram...................................................................................................... 621
19.1.3 Input and Output Pins........................................................................................... 623
19.1.4 Register Configuration ......................................................................................... 623
19.2 Register Descriptions......................................................................................................... 624
19.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1).................................................. 624
19.2.2 D/A Control Register (DACR)............................................................................. 624
19.2.3 Module Stop Control Register (MSTPCR) .......................................................... 626
19.3 Operation ........................................................................................................................... 627
Section 20 A/D Converter ................................................................................................. 629
20.1 Overview............................................................................................................................ 629
20.1.1 Features ................................................................................................................ 629
20.1.2 Block Diagram...................................................................................................... 630
20.1.3 Pin Configuration ................................................................................................. 631
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