HD64F2149 Datasheet, PDF (522/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bits 2 to 0—Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be
transferred next. With the I²C bus format (when the FS bit in SAR or the FSX bit in SARX is 0),
the data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made
during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000,
the setting should be made while the SCL line is low.
The bit counter is initialized to 000 by a reset and when a start condition is detected. The value
returns to 000 at the end of a data transfer, including the acknowledge bit.
Bit 2
BC2
0
1
Bit 1
BC1
0
1
0
1
Bit 0
BC0
0
1
0
1
0
1
0
1
Bits/Frame
Synchronous Serial Format I²C Bus Format
8
9
(Initial value)
1
2
2
3
3
4
4
5
5
6
6
7
7
8
16.2.5 I²C Bus Control Register (ICCR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
ICE
IEIC MST TRS ACKE BBSY IRIC SCP
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W R/(W)* W
Note: * Only 0 can be written, to clear the flag.
ICCR is an 8-bit readable/writable register that enables or disables the I²C bus interface, enables or
disables interrupts, selects master or slave mode and transmission or reception, enables or disables
acknowledgement, confirms the I²C bus interface bus status, issues start/stop conditions, and
performs interrupt flag confirmation.
ICCR is initialized to H'01 by a reset and in hardware standby mode.
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