HD64F2149 Datasheet, PDF (508/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Restrictions on Use of DTC
• When an external clock source is used as the serial clock, the transmit clock should not be
input until at least 5 ø clock cycles after TDR is updated by the DTC. Misoperation may occur
if the transmit clock is input within 4 clock cycles after TDR is updated. (Figure 15.24)
• When RDR is read by the DTC, be sure to set the activation source to the relevant SCI receive-
data-full interrupt (RXI).
SCK
TDRE
Serial data
t
LSB
D0
D1
D2
D3
D4
D5
D6
D7
Note: When operating on an external clock, set t > 4 states.
Figure 15.24 Example of Synchronous Transmission by DTC
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