HD64F2149 Datasheet, PDF (152/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

• Program area in on-chip memory, 1-state execution instruction at specified break address
Instruction Instruction Instruction Instruction Instruction Internal
fetch
fetch
fetch
fetch
fetch operation
Stack save
Vector Internal Instruction
fetch operation fetch
ø
Address bus
H'0310 H'0312 H'0314 H'0316
H'0318
SP-2 SP-4
H'0036
NOP
NOP
NOP
execution execution execution
Interrupt exception handling
Break request
signal
H'0310 NOP
H'0312 NOP
H'0314 NOP
H'0316 NOP
Breakpoint NOP instruction is executed at breakpoint address H'0312 and
next address, H'0314; fetch from address H'0316 starts after
end of exception handling.
• Program area in on-chip memory, 2-state execution instruction at specified break address
Instruction Instruction Instruction Instruction Instruction Internal
fetch
fetch
fetch
fetch
fetch operation
Stack save
Vector Internal Instruction
fetch operation fetch
ø
Address bus
H'0310 H'0312 H'0314 H'0316
H'0318
SP-2 SP-4
H'0036
NOP
execution
Break request
signal
H'0310 NOP
H'0312 MOV.W #xx:16,Rd
H'0316 NOP
H'0318 NOP
MOV.W
execution
Interrupt exception handling
Breakpoint MOV instruction is executed at breakpoint address H'0312,
NOP instruction at next address, H'0316, is not executed;
fetch from address H'0316 starts after end of exception handling.
• Program area in external memory (2-state access, 16-bit-bus access),
1-state execution instruction at specified break address
Instruction
fetch
Instruction
fetch
Instruction
fetch
Internal
operation
Stack save
Vector
fetch
Internal
operation
ø
Address bus
H'0310
H'0312
H'0314
SP-2 SP-4
H'0036
Break request
signal
118
NOP
execution
Interrupt exception handling
H'0310 NOP
H'0312 NOP
H'0314 NOP
H'0316 NOP
Breakpoint NOP instruction at breakpoint address H'0312 is not executed;
fetch from address H'0312 starts after end of exception handling.
Figure 5.6 Examples of Address Break Timing