HD64F2149 Datasheet, PDF (551/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

• A common data pin (SDA) for formatless and I²C bus format operation
• Separate clock pins for formatless operation (VSYNCI) and I²C bus format operation (SCL)
• A fixed 1 level for the SCL pin during formatless operation (the SCL pin does not output a low
level)
• Settings of bits other than TRS in ICCR that allow I²C bus format operation
Automatic switching is performed from formatless mode to the I²C bus format when the SW bit in
DDCSWR is automatically cleared to 0 on detection of a falling edge on the SCL pin. Switching
from the I²C bus format to formatless mode is achieved by having software set the SW bit in
DDCSWR to 1.
In formatless mode, bits (such as MSL and TRS) that control the I²C bus interface operating mode
must not be modified. When switching from the I²C bus format to formatless mode, set the TRS
bit to 1 or clear it to 0 according to the transmit data (transmission or reception) in formatless
mode, then set the SW bit to 1. After automatic switching from formatless mode to the I²C bus
format (slave mode), in order to wait for slave address reception, the TRS bit is automatically
cleared to 0.
If a falling edge is detected on the SCL pin during formatless operation, I²C bus interface
operation is deferred until a stop condition is detected.
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