HD64F2149 Datasheet, PDF (632/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

SIRQCR1 Bit 7—HIRQ11 Interrupt Enable 3 (IRQ11E3): Enables or disables a HIRQ11
interrupt request when OBF3A is set by an ODR3 write.
Bit 7
IRQ11E3
0
1
Description
HIRQ11 interrupt request by OBF3A and IRQ11E3 is disabled (Initial value)
[Clearing conditions]
• Writing 0 to IRQ11E3
• LPC hardware reset, LPC software reset
• Clearing OBF3A to 0 (when IEDIR = 0)
[When IEDIR = 0]
HIRQ11 interrupt request by setting OBF3A to 1 is enabled
[When IEDIR = 1]
HIRQ11 interrupt is requested
[Setting condition]
• Writing 1 after reading IRQ11E3 = 0
SIRQCR1 Bit 6—HIRQ10 Interrupt Enable 3 (IRQ10E3): Enables or disables a HIRQ10
interrupt request when OBF3A is set by an ODR3 write.
Bit 6
IRQ10E3
0
1
Description
HIRQ10 interrupt request by OBF3A and IRQ10E3 is disabled (Initial value)
[Clearing conditions]
• Writing 0 to IRQ10E3
• LPC hardware reset, LPC software reset
• Clearing OBF3A to 0 (when IEDIR = 0)
[When IEDIR = 0]
HIRQ10 interrupt request by setting OBF3A to 1 is enabled
[When IEDIR = 1]
HIRQ10 interrupt is requested
[Setting condition]
• Writing 1 after reading IRQ10E3 = 0
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