HD64F2149 Datasheet, PDF (344/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 6
IEDGB
0
1
Description
Capture on the falling edge of FTIB
Capture on the rising edge of FTIB
(Initial value)
Bit 5—Input Edge Select C (IEDGC): Selects the rising or falling edge of the input capture C
signal (FTIC).
Bit 5
IEDGC
0
1
Description
Capture on the falling edge of FTIC
Capture on the rising edge of FTIC
(Initial value)
Bit 4—Input Edge Select D (IEDGD): Selects the rising or falling edge of the input capture D
signal (FTID).
Bit 4
IEDGD
0
1
Description
Capture on the falling edge of FTID
Capture on the rising edge of FTID
(Initial value)
Bit 3—Buffer Enable A (BUFEA): Selects whether ICRC is to be used as a buffer register for
ICRA.
Bit 3
BUFEA
0
1
Description
ICRC is not used as a buffer register for input capture A
ICRC is used as a buffer register for input capture A
(Initial value)
Bit 2—Buffer Enable B (BUFEB): Selects whether ICRD is to be used as a buffer register for
ICRB.
Bit 2
BUFEB
0
1
Description
ICRD is not used as a buffer register for input capture B
ICRD is used as a buffer register for input capture B
(Initial value)
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