HD64F2149 Datasheet, PDF (367/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the upper 8 bits
for channel 0 and the lower 8 bits for channel 1, so they can be accessed together by word access.
(Access is not divided into two 8-bit accesses.)
In the H8S/2169 or H8S/2149, certain of the channel X and channel Y registers are assigned to the
same address. The TMRX/Y bit in TCONRS determines which register is accessed.
12.2 Register Descriptions
12.2.1 Timer Counter (TCNT)
TCNT0
TCNT1
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCNTX,TCNTY
Bit
7
6
5
4
3
2
1
0
Initial value
0
Read/Write R/W
0
0
R/W R/W
0
0
0
R/W R/W R/W
0
0
R/W R/W
Each TCNT is an 8-bit readable/writable up-counter.
TCNT0 and TCNT1 comprise a single 16-bit register, so they can be accessed together by word
access.
TCNT increments on pulses generated from an internal or external clock source. This clock source
is selected by clock select bits CKS2 to CKS0 in TCR.
TCNT can be cleared by an external reset input signal or compare-match signal. Counter clear bits
CCLR1 and CCLR0 in TCR select the method of clearing.
When TCNT overflows from H'FF to H'00, the overflow flag (OVF) in TCSR is set to 1.
The timer counters are initialized to H'00 by a reset and in hardware standby mode.
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