HD64F2149 Datasheet, PDF (107/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

2.9.4 On-Chip Supporting Module Access Timing (Internal I/O Register 3)
The on-chip supporting modules (internal I/O register 3) are accessed in three states. The data bus
is 8 bits wide. Figure 2.21 shows the access timing fo the on-chip supporting modules (internal I/O
register 3). Figure 2.22 shows the pin states.
Bus cycle
T1
T2
T3
φ
Internal address bus
Address
Read
access
Write
access
Internal read
signal
Internal data
bus
Internal write
signal
Internal data
bus
Read data
Write data
Figure 2.21 On-Chip Supporting Module (Internal I/O Register 3) Access Cycle
Bus cycle
T1
T2
T3
φ
Address bus
Unchanged
AS
High
RD
HWR, LWR
Data bus
High
High
High impedance
Figure 2.22 Pin States during On-Chip Supporting Module (Internal I/O Register 3) Access
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