HD64F2149 Datasheet, PDF (323/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 1—Output Select (OS): Selects the phase of the PWM (D/A) output.
Bit 1
OS
0
1
Description
Direct PWM output
Inverted PWM output
(Initial value)
Bit 0—Clock Select (CKS): Selects the PWM (D/A) resolution. If the system clock (ø) frequency
is 10 MHz, resolutions of 100 ns and 200 ns can be selected.
Bit 0
CKS
0
1
Description
Operates at resolution (T) = system clock cycle time (t_cyc)
Operates at resolution (T) = system clock cycle time (t_cyc) × 2
(Initial value)
10.2.4 Module Stop Control Register (MSTPCR)
MSTPCRH
MSTPCRL
Bit
7654321076543210
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop
mode control.
When the MSTP11 bit is set to 1, 14-bit PWM timer operation is halted and a transition is made to
module stop mode. For details, see section 24.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 3—Module Stop (MSTP11): Specifies PWMX module stop mode.
MSTPCRH
Bit 3
MSTP11 Description
0
PWMX module stop mode is cleared
1
PWMX module stop mode is set
(Initial value)
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