HD64F2149 Datasheet, PDF (173/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 4
BRSTS1
0
1
Description
Burst cycle comprises 1 state
Burst cycle comprises 2 states
(Initial value)
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 3
BRSTS0
0
1
Description
Max. 4 words in burst access
Max. 8 words in burst access
(Initial value)
Bit 2—Reserved: Do not write 0 to this bit.
Bits 1 and 0—IOS Select 1 and 0 (IOS1, IOS0): See table 6.4.
6.2.2 Wait State Control Register (WSCR)
Bit
Initial value
Read/Write
7
RAMS
0
R/W
6
RAM0
0
R/W
5
ABW
1
R/W
4
3
2
1
AST WMS1 WMS0 WC1
1
0
0
1
R/W R/W R/W R/W
0
WC0
1
R/W
WSCR is an 8-bit readable/writable register that specifies the data bus width, number of access
states, wait mode, and number of wait states for external memory space. The on-chip memory and
internal I/O register bus width and number of access states are fixed, irrespective of the WSCR
settings.
WSCR is initialized to H'33 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—RAM Select (RAMS)/Bit 6—RAM Area Setting (RAM0): Reserved bits. Do not write
1 to these bits.
Bit 5—Bus Width Control (ABW): Specifies whether the external memory space is 8-bit access
space or 16-bit access space.
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