HD64F2149 Datasheet, PDF (639/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

event of a transfer cycle forced termination (abort) before state #12, registers and flags are not
changed.
State
Count
1
2
3
4
5
6
7
8
9
10
11
12
13
I/O Read Cycle
Contents
Drive Value
Source (3 to 0)
Start
Host 0000
Cycle type/direction Host 0000
Address 1
Host
Bits 15 to
12
Address 2
Host Bits 11 to 8
Address 3
Host Bits 7 to 4
Address 4
Host Bits 3 to 0
Turnaround
(recovery)
Host 1111
Turnaround
None ZZZZ
Synchronization Slave 0000
Data 1
Data 2
Turnaround
(recovery)
Turnaround
Slave
Slave
Slave
Bits 3 to 0
Bits 7 to 4
1111
None ZZZZ
I/O Write Cycle
Contents
Drive Value
Source (3 to 0)
Start
Host 0000
Cycle type/direction Host 0010
Address 1
Host
Bits 15 to
12
Address 2
Host Bits 11 to 8
Address 3
Host Bits 7 to 4
Address 4
Host Bits 3 to 0
Data 1
Host Bits 3 to 0
Data 2
Turnaround
(recovery)
Turnaround
Synchronization
Turnaround
(recovery)
Turnaround
Host
Host
Bits 7 to 4
1111
None
Slave
Slave
ZZZZ
0000
1111
None ZZZZ
The timing of the LFRAME, LCLK, and LAD signals is shown in figures 18B.2 and 18B.3.
LCLK
LFRAME
LAD3–LAD0
Start
ADDR TAR Sync Data TAR Start
Cycle type,
direction,
and size
Number of clocks ¹
1
4
2
1
2
2
1
Figure 18B.2 Typical LFRAME Timing
605