HD64F2149 Datasheet, PDF (564/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

• Notes on I²C Bus Interface Stop Condition Instruction Issuance
If the rise time of the 9th SCL clock exceeds the specification because the bus load capacitance
is large, or if there is a slave device of the type that drives SCL low to effect a wait, after rising
of the 9th SCL clock, issue the stop condition after reading SCL and determining it to below,
as shown below.
SCL
SDA
IRIC
9th clock
VIH
High period secured
As waveform rise is late,
SCL is detected as low
Stop condition
generation
[1] Determination of SCL = Low
[2] Stop condition instruction isuuance
Figure 16.20 Timing of Stop Condition Issuance
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