HD64F2149 Datasheet, PDF (899/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

HICR0—Host Interface Control Register 0
H'FE40
HIF (LPC)
Bit
Initial value
Slave Read/Write
Host Read/Write
7
LPC3E
0
R/W
—
6
LPC2E
0
R/W
—
5
4
3
LPC1E FGA20E SDWNE
0
0
0
R/W R/W R/W
—
—
—
2
PMEE
0
R/W
—
1
LSMIE
0
R/W
—
0
LSCIE
0
R/W
—
LSCI output enable
HICR0 HICR1
Bit 0 Bit 0
Description
LSCIE LSCIB
0
0 LSCI output disabled, other function of pin enabled
1 LSCI output disabled, other function of pin enabled
1
0 LSCI output enabled, LSCI pin output goes to 0 level
1 LSCI output enabled, LSCI pin output is high-impedance
LSMI output enable
HICR0 HICR1
Bit 1 Bit 1
LSMIE LSMIB
Description
0
0 LSMI output disabled, other function of pin enabled
1 LSMI output disabled, other function of pin enabled
1
0 LSMI output enabled, LSMI pin output goes to 0 level
1 LSMI output enabled, LSMI pin output is high-impedance
PME output enable
HICR0 HICR1
Bit 2 Bit 2
PMEE PMEB
Description
0
0 PME output disabled, other function of pin enabled
1 PME output disabled, other function of pin enabled
1
0 PME output enabled, PME pin output goes to 0 level
1 PME output enabled, PME pin output is high-impedance
LPC software shutdown enable
0 Normal state, LPC software shutdown setting enabled
[Clearing conditions]
• Writing 0
• LPC hardware reset or LPC software reset
• LPC hardware shutdown release (rising edge of LPCPD signal)
1 LPC hardware shutdown state setting enabled
Hardware shutdown state when LPCPD signal is low
[Setting condition]
• Writing 1 after reading SDWNE = 0
Fast GATE A20 enable
0 Fast GATE A20 function is disabled
• Other function of pin is enabled
• GA20 output internal state is initialized to 1
1 Fast GATE A20 function is enabled
• GA20 pin output is open-drain (external VCC pull-up resistor required)
LPC enable 1
0 LPC channel 1 operation is disabled
No address (H'0060, 64) matches for IDR1, ODR1, or STR1
LPC enable 2
1 LPC channel 1 operation is enabled
0 LPC channel 2 operation is disabled
No address (H'0062, 66) matches for IDR2, ODR2, or STR2
1 LPC channel 2 operation is enabled
LPC enable 3
0 LPC channel 3 operation is disabled
No address (LADR3) matches for IDR3, ODR3, STR3, or TWR0 to TWR15
1 LPC channel 3 operation is enabled
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