HD64F2149 Datasheet, PDF (406/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bits 3 and 2—Vertical Synchronization Output Mode Select 1 and 0 (VOMOD1, VOMOD0):
These bits select the signal source and generation method for the IVO signal.
Bit 6
ISGENE
0
1
Bit 3
VOMOD1
0
Bit 2
VOMOD0
0
1
1
0
1
0
0
1
1
0
1
Description
The IVI signal (without fall modification
or IHI synchronization) is selected
(Initial value)
The IVI signal (without fall modification, with IHI
synchronization) is selected
The IVI signal (with fall modification, without IHI
synchronization) is selected
The IVI signal (with fall modification and IHI
synchronization) is selected
The IVG signal is selected
Bits 1 and 0—Clamp Waveform Mode Select 1 and 0 (CLMOD1, CLMOD0): These bits
select the signal source for the CLO signal (clamp waveform).
Bit 6
ISGENE
0
1
Bit 1
CLMOD1
0
1
0
1
Bit 0
CLMOD2
0
1
0
1
0
1
0
1
Description
The CL1 signal is selected
The CL2 signal is selected
The CL3 signal is selected
The CL4 signal is selected
(Initial value)
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