HD64F2149 Datasheet, PDF (895/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

STR1—Status Register 1
STR2—Status Register 2
H'FE3A
H'FE3E
• STR1
Bit
Initial value
Slave Read/Write
Host Read/Write
7
DBU17
0
R/W
R
6
DBU16
0
R/W
R
5
DBU15
0
R/W
R
4
DBU14
0
R/W
R
3
C/D1
0
R
R
2
DBU12
0
R/W
R
• STR2
Bit
Initial value
Slave Read/Write
Host Read/Write
7
DBU27
0
R/W
R
6
DBU26
0
R/W
R
5
DBU25
0
R/W
R
4
DBU24
0
R/W
R
3
C/D2
0
R
R
2
DBU22
0
R/W
R
HIF (LPC)
HIF (LPC)
1
IBF1
0
R
R
0
OBF1
0
R/(W)*
R
1
IBF2
0
R
R
0
OBF2
0
R/(W)*
R
User-defined bits
Output data register full
0 [Clearing condition]
Host reads ODR using I/O read cycle,
or slave writes 0 to OBF bit
1 [Setting condition]
Slave writes to ODR
Input data register full
0 [Clearing condition]
Slave reads IDR
1 [Setting condition]
Host writes to IDR using I/O write cycle
Command/data
0 Input data register (IDR) contents are data
1 Input data register (IDR) contents are a command
Note: * Only 0 can be written, to clear the flag.
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