HD64F2149 Datasheet, PDF (559/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

16.4 Usage Notes
• In master mode, if an instruction to generate a start condition is immediately followed by an
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions, after issuing the instruction that generates the start
condition, read the relevant ports, check that SCL and SDA are both low, then issue the
instruction that generates the stop condition. Note that SCL may not yet have gone low when
BBSY is cleared to 0.
• Either of the following two conditions will start the next transfer. Pay attention to these
conditions when reading or writing to ICDR.
 Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from
ICDRT to ICDRS)
 Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from
ICDRS to ICDRR)
• Table 16.6 shows the timing of SCL and SDA output in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
Table 16.6 I²C Bus Timing (SCL and SDA Output)
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Symbol
t _SCLO
t _SCLHO
t _SCLLO
t _BUFO
t _STAHO
t _STASO
t _STOSO
t _SDASO
Data output hold time
t _SDAHO
Note: * 6t_cyc when IICX is 0, 12t_cyc when 1.
Output Timing
28t_cyc to 256t_cyc
0.5t_SCLO
0.5t_SCLO
0.5t_SCLO – 1t_cyc
0.5t_SCLO – 1t_cyc
1t _SCLO
0.5t_SCLO + 2t_cyc
1t_SCLLO – 3t_cyc
1t_SCLL – (6t_cyc or
12t_cyc*)
3t _cyc
Unit Notes
ns
Figure 25.27
ns
(reference)
ns
ns
ns
ns
ns
ns
ns
• SCL and SDA input is sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t_cyc, as shown in I²C bus Timing in section 25,
Electrical Characteristics. Note that the I²C bus interface AC timing specifications will not be
met with a system clock frequency of less than 5 MHz.
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