HD64F2149 Datasheet, PDF (197/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

7.1.3 Register Configuration
Table 7.1 summarizes the DTC registers.
Table 7.1 DTC Registers
Name
Abbreviation R/W Initial Value Address*¹
DTC mode register A
MRA
—*² Undefined
—*³
DTC mode register B
MRB
—*² Undefined
—*³
DTC source address register
SAR
—*² Undefined
—*³
DTC destination address register DAR
—*² Undefined
—*³
DTC transfer count register A
CRA
—*² Undefined
—*³
DTC transfer count register B
CRB
—*² Undefined
—*³
DTC enable registers
DTCER
R/W H'00
H'FEEE to H'FEF2
DTC vector register
DTVECR
R/W H'00
H'FEF3
Module stop control register
MSTPCRH R/W H'3F
H'FF86
MSTPCRL R/W H'FF
H'FF87
Notes: 1. Lower 16 bits of the address.
2. Registers within the DTC cannot be read or written to directly.
3. Allocated to on-chip RAM addresses H'EC00 to H'EFFF as register information.
They cannot be located in external memory space.
When the DTC is used, do not clear the RAME bit in SYSCR to 0.
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