HD64F2149 Datasheet, PDF (624/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

The IDR registers are 8-bit read-only registers to the slave processor, and 8-bit write-only registers
to the host processor. The registers selected from the host according to the I/O address are shown
in the following table. For information on IDR3 selection, see section 18B.2.4, LPC Channel 3
Address Register (LADR3). Data transferred in an LPC I/O write cycle is written to the selected
register. The state of bit 2 of the I/O address is latched into the C/D bit in STR, to indicate whether
the written information is a command or data.
The initial values of the IDR registers after a reset and in standby mode are undetermined.
Bits 15 to 4
0000 0000 0110
0000 0000 0110
0000 0000 0110
0000 0000 0110
I/O Address
Bit 3 Bit 2
0
0
0
1
0
0
0
1
Bit 1
0
0
1
1
Bit 0
0
0
0
0
Transfer
Cycle
I/O write
I/O write
I/O write
I/O write
Host Register Selection
IDR1 write, C/D1 ← 0
IDR1 write, C/D1 ← 1
IDR2 write, C/D2 ← 0
IDR2 write, C/D2 ← 1
18B.2.6 Output Data Registers (ODR1, ODR2, ODR3)
Bit
Initial value
Slave Read/Write
Host Read/Write
7
Bit 7
—
R/W
R
6
Bit 6
—
R/W
R
5
Bit 5
—
R/W
R
4
Bit 4
—
R/W
R
3
Bit 3
—
R/W
R
2
Bit 2
—
R/W
R
1
Bit 1
—
R/W
R
0
Bit 0
—
R/W
R
The ODR registers are 8-bit readable/writable registers to the slave processor, and 8-bit read-only
registers to the host processor. The registers selected from the host according to the I/O address
are shown in the following table. For information on ODR3 selection, see section 18B.2.4, LPC
Channel 3 Address Register (LADR3). In an LPC I/O read cycle, the data in the selected register
is transferred to the host.
The initial values of the ODR registers after a reset and in standby mode are undetermined.
Bits 15 to 4
0000 0000 0110
0000 0000 0110
I/O Address
Bit 3 Bit 2
0
0
0
0
Bit 1
0
1
Bit 0
0
0
Transfer
Cycle
I/O read
I/O read
Host Register Selection
ODR1 read
ODR2 read
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