HD64F2149 Datasheet, PDF (357/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

11.6 Usage Notes
Application programmers should note that the following types of contention can occur in the free-
running timer.
Contention between FRC Write and Clear: If an internal counter clear signal is generated
during the state after an FRC write cycle, the clear signal takes priority and the write is not
performed.
Figure 11.18 shows this type of contention.
FRC write cycle
T₁
T₂
ø
Address
FRC address
Internal write
signal
Counter clear
signal
FRC
N
H'0000
Figure 11.18 FRC Write-Clear Contention
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