HD64F2149 Datasheet, PDF (452/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format
is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in
asynchronous mode; it is invalid in synchronous mode.
For details of the multiprocessor communication function, see section 15.3.3, Multiprocessor
Communication Function.
Bit 2
MP
0
1
Description
Multiprocessor function disabled
Multiprocessor format selected
(Initial value)
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the
baud rate generator. The clock source can be selected from ø, ø/4, ø/16, and ø/64, according to the
setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 15.2.8, Bit Rate Register.
Bit 1
CKS1
0
1
Bit 0
CKS0
0
1
0
1
Description
ø clock
ø/4 clock
ø/16 clock
ø/64 clock
(Initial value)
15.2.6 Serial Control Register (SCR)
Bit
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE MPIE TEIE CKE1 CKE0
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output
in asynchronous mode, and interrupt requests, and selection of the serial clock source.
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