HD64F2149 Datasheet, PDF (339/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 6—Input Capture Interrupt B Enable (ICIBE): Selects whether to request input capture
interrupt B (ICIB) when input capture flag B (ICFB) in TCSR is set to 1.
Bit 6
ICIBE
0
1
Description
Input capture interrupt request B (ICIB) is disabled
Input capture interrupt request B (ICIB) is enabled
(Initial value)
Bit 5—Input Capture Interrupt C Enable (ICICE): Selects whether to request input capture
interrupt C (ICIC) when input capture flag C (ICFC) in TCSR is set to 1.
Bit 5
ICICE
0
1
Description
Input capture interrupt request C (ICIC) is disabled
Input capture interrupt request C (ICIC) is enabled
(Initial value)
Bit 4—Input Capture Interrupt D Enable (ICIDE): Selects whether to request input capture
interrupt D (ICID) when input capture flag D (ICFD) in TCSR is set to 1.
Bit 4
ICIDE
0
1
Description
Input capture interrupt request D (ICID) is disabled
Input capture interrupt request D (ICID) is enabled
(Initial value)
Bit 3—Output Compare Interrupt A Enable (OCIAE): Selects whether to request output
compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1.
Bit 3
OCIAE
0
1
Description
Output compare interrupt request A (OCIA) is disabled
Output compare interrupt request A (OCIA) is enabled
(Initial value)
Bit 2—Output Compare Interrupt B Enable (OCIBE): Selects whether to request output
compare interrupt B (OCIB) when output compare flag B (OCFB) in TCSR is set to 1.
Bit 2
OCIBE
0
1
Description
Output compare interrupt request B (OCIB) is disabled
Output compare interrupt request B (OCIB) is enabled
(Initial value)
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