HD64F2149 Datasheet, PDF (820/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

8. Block Transfer Instruction
Addressing Mode and
Instruction Length (Bytes)
Mnemonic
Operation
Condition Code
No. of
States^*1
I HNZVC
EEPMOV EEPMOV.B
—
EEPMOV.W
—
4 if R4L≠0
Repeat @ER5→@ER6
ER5+1→ER5
ER6+1→ER6
R4L-1→R4L
Until R4L=0
else next;
4 if R4≠0
Repeat @ER5→@ER6
ER5+1→ER5
ER6+1→ER6
R4-1→R4
Until R4=0
else next;
— — — — — — 4+2n^*3
— — — — — — 4+2n^*3
Notes: 1. The number of states is the number of states required for execution when the
instruction and its operands are located in on-chip memory.
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
3. n is the initial value set in R4L or R4.
4. Only registers ER0 to ER6 should be used when using the STM/LDM instruction.
[1] 7 states when the number of saved/restored registers is 2, 9 states when 3, and 11
states when 4.
[2] Cannot be used with the LSI.
[3] Set to 1 when there is a carry from or borrow to bit 11; otherwise cleared to 0.
[4] Set to 1 when there is a carry from or borrow to bit 27; otherwise cleared to 0.
[5] If the result is zero, the previous value of the flag is retained; otherwise the flag is
cleared to 0.
[6] Set to 1 if the divisor is negative; otherwise cleared to 0.
[7] Set to 1 if the divisor is zero; otherwise cleared to 0.
[8] Set to 1 if the quotient is negative; otherwise cleared to 0.
[9] When EXR is valid, the number of states is increased by 1.
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