HD64F2149 Datasheet, PDF (904/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

IDR3—Input Data Register 3
IDR4—Input Data Register 4
Bit
Initial value
Slave R/W
Host R/W
7
IDR7
—
R
W
6
IDR6
—
R
W
5
IDR5
—
R
W
H'FE84
H'FE8C
4
IDR4
—
R
W
3
IDR3
—
R
W
2
IDR2
—
R
W
HIF (XBS)
HIF (XBS)
1
IDR1
—
R
W
0
IDR0
—
R
W
Stores host data bus contents at rise of IOW when CS is low
ODR3—Output Data Register 3
ODR4—Output Data Register 4
Bit
Initial value
Slave R/W
Host R/W
7
ODR7
—
R/W
R
6
ODR6
—
R/W
R
5
ODR5
—
R/W
R
4
ODR4
—
R/W
R
H'FE85
H'FE8D
3
ODR3
—
R/W
R
2
ODR2
—
R/W
R
1
ODR1
—
R/W
R
HIF (XBS)
HIF (XBS)
0
ODR0
—
R/W
R
ODR contents are output to the host data bus
when HA0 is low, CS is low, and IOR is low
870