HD64F2149 Datasheet, PDF (945/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

TCSR0—Timer Control/Status Register 0
H'FFA8
TCSR0
Bit
Initial value
Read/Write
7
OVF
0
R/(W)*
6
WT/IT
0
R/W
5
TME
0
R/W
4
3
2
RSTS RST/NMI CKS2
0
0
0
R/W R/W R/W
1
CKS1
0
R/W
WDT0
0
CKS0
0
R/W
Clock select 2 to 0
CKS2 CKS1 CKS0 Clock
0
0
0 ø/2
1 ø/64
1
0 ø/128
1 ø/512
1
0
0 ø/2048
1 ø/8192
1
0 ø/32768
1 ø/131072
Reset or NMI
0 NMI interrupt requested
1 Internal reset requested
Reserved bit
Timer enable
0 TCNT is initialized to H'00 and halted
1 TCNT counts
Timer mode select
0 Interval timer mode: Sends the CPU an interval timer interrupt
request (WOVI) when TCNT overflows
1 Watchdog timer mode: Generates a reset or NMI interrupt when
TCNT overflows
RESO pin output goes low simultaneously (when internal reset
is selected)
Overflow flag
0 [Clearing conditions]
• Write 0 in the TME bit
• Read TCSR when OVF = 1, then write 0 in OVF
1 [Setting condition]
When TCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog
timer mode, OVF is cleared automatically by the internal reset.)
Note: * Only 0 can be written, to clear the flag.
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