HD64F2149 Datasheet, PDF (735/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Section 23 Clock Pulse Generator
23.1 Overview
The H8S/2169 and H8S/2149 have a built-in clock pulse generator (CPG) that generates the
system clock (ø), the bus master clock, and internal clocks.
The clock pulse generator consists of an oscillator circuit, a duty-cycle adjustment circuit, clock
selection circuit, medium-speed clock divider, bus-master clock selection circuit, subclock input
circuit, and waveform shaping circuit.
23.1.1 Block Diagram
Figure 23.1 is a block diagram of the clock pulse generator.
EXTAL
XTAL
Oscillator
Duty-cycle
adjustment
circuit
ø_SUB
Clock
selection
circuit
Medium-speed
clock divider _{ø/2 to ø/32}
Bus-master
clock
selection
circuit
ø
EXCL
Subclock
input circuit
Waveform
shaping
circuit
System clock
To ø pin
Internal clock
To supporting
modules
WDT1 count clock
Figure 23.1 Block Diagram of Clock Pulse Generator
Bus master clock
To CPU, DTC
23.1.2 Register Configuration
The clock pulse generator is controlled by the standby control register (SBYCR) and low-power
control register (LPWRCR). Table 23.1 shows the register configuration.
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