HD64F2149 Datasheet, PDF (752/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 7
DTON
Description
0
When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode, software standby mode, or watch mode*
When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode or watch mode
(Initial value)
1
When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made directly to subactive mode*, or a transition is made to sleep mode
or software standby mode
When a SLEEP instruction is executed in subactive mode, a transition is made directly
to high-speed mode, or a transition is made to subsleep mode
Note: * When a transition is made to watch mode or subactive mode, high-speed mode must be
set.
Bit 6—Low-Speed On Flag (LSON): Determines the operating mode in combination with other
control bits when making a power-down transition by executing a SLEEP instruction. Also
controls whether a transition is made to high-speed mode or to subactive mode when watch mode
is cleared.
Bit 6
LSON
Description
0
When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode, software standby mode, or watch mode*
When a SLEEP instruction is executed in subactive mode, a transition is made to
watch mode, or directly to high-speed mode
After watch mode is cleared, a transition is made to high-speed mode (Initial value)
1
When a SLEEP instruction is executed in high-speed mode a transition is made to
watch mode or subactive mode*
When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode or watch mode
After watch mode is cleared, a transition is made to subactive mode
Note: * When a transition is made to watch mode or subactive mode, high-speed mode must be
set.
Bit 5—Noise Elimination Sampling Frequency Select (NESEL): Selects the frequency at which
the subclock (øSUB) input from the EXCL pin is sampled with the clock (ø) generated by the
system clock oscillator. When ø = 5 MHz or higher, clear this bit to 0.
718