HD64F2149 Datasheet, PDF (619/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

18B.2.3 Host Interface Control Registers 2 and 3 (HICR2, HICR3)
• HICR2
Bit
Initial value
Slave Read/Write
Host Read/Write
7
GA20
0
R
—
6
LRST
0
R/(W)*
—
5
SDWN
0
R/(W)*
—
4
ABRT
0
R/(W)*
—
3
IBFIE3
0
R/W
—
2
IBFIE2
0
R/W
—
1
IBFIE1
0
R/W
—
0
ERRIE
0
R/W
—
Note: * Only 0 can be written to bits 6 to 4, to clear the flags.
• HICR3
Bit
7
6
5
4
3
LFRAME CLKRUN SERIRQ LRESET LPCPD
Initial value
0
0
0
0
0
Slave Read/Write R
R
R
R
R
Host Read/Write
—
—
—
—
—
2
PME
0
R
—
1
LSMI
0
R
—
0
LSCI
0
R
—
HICR2 and HICR3 contain flags and bits that control interrupts from the host interface (LPC)
module to the slave processor, and bits that monitor host interface pin states.
Bits 6 to 0 of HICR2 are initialized to H'00 by a reset and in hardware standby mode. The states of
the other bits are determined by the pin states.
HICR2 Bit 7—GA20 Pin Monitor (GA20)
HICR3 Bit 7—LFRAME Pin Monitor (LFRAME)
HICR3 Bit 6—CLKRUN Pin Monitor (CLKRUN)
HICR3 Bit 5—SERIRQ Pin Monitor (SERIRQ)
HICR3 Bit 4—LRESET Pin Monitor (LRESET)
HICR3 Bit 3—LPCPD Pin Monitor (LPCPD)
HICR3 Bit 2—PME Pin Monitor (PME)
HICR3 Bit 1—LSMI Pin Monitor (LSMI)
HICR3 Bit 0—LSCI Pin Monitor (LSCI)
These are pin state monitoring bits. The pin states can be monitored regardless of the host
interface operating state or the operating state of the functions that use pin multiplexing.
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