HD64F2149 Datasheet, PDF (977/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

TCONRI—Timer Connection Register I
H'FFFC
Timer Connection
Bit
7
6
5
SIMOD1 SIMOD0 SCONE
Initial value 0
0
0
Read/Write R/W
R/W R/W
4
ICST
0
R/W
3
HFINV
0
R/W
2
VFINV
0
R/W
1
HIINV
0
R/W
0
VIINV
0
R/W
Input synchronization
signal inversion
0 The VSYNCI pin state
is used directly as
the VSYNCI input
1 The VSYNCI pin state
is inverted before use
as the VSYNCI input
Input synchronization signal inversion
0 The HSYNCI and CSYNCI pin states are used
directly as the HSYNCI and CSYNCI inputs
1 The HSYNCI and CSYNCI pin states are inverted
before use as the HSYNCI and CSYNCI inputs
Input synchronization signal inversion
0 The VFBACKI pin state is used directly as the VFBACKI input
1 The VFBACKI pin state is inverted before use as the VFBACKI input
Input synchronization signal inversion
0 The HFBACKI pin state is used directly as the HFBACKI input
1 The HFBACKI pin state is inverted before use as the HFBACKI input
Input capture start bit
0 The TICRR and TICRF input capture functions are stopped
[Clearing condition]
When a rising edge followed by a falling edge is detected on TMRIX
1 The TICRR and TICRF input capture functions are operating
(Waiting for detection of a rising edge followed by a falling edge on TMRIX)
[Setting condition]
When 1 is written in ICST after reading ICST = 0
Synchronization signal connection enable
SCONE
Mode
FTIA FTIB
0
Normal
connection
FTIA
input
FTIB
input
1
Synchronization IVI
TMO1
signal connec- signal signal
tion mode
FTIC
FTIC
input
VFBACKI
input
FTID
FTID
input
IHI
signal
TMCI1
TMCI1
input
IHI
signal
TMRI1
TMRI1
input
IVI
inverse
signal
Input synchronization mode select 1 and 0
SIMOD1 SIMOD0
Mode
0
0
No signal
1
S-on-G mode
1
0
Composite mode
1
Separate mode
IHI signal
HFBACKI input
CSYNCI input
HSYNCI input
HSYNCI input
IVI signal
VFBACKI input
PDC input
PDC input
VSYNCI input
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