HD64F2149 Datasheet, PDF (172/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

6.2 Register Descriptions
6.2.1 Bus Control Register (BCR)
Bit
Initial value
Read/Write
7
ICIS1
1
R/W
6
5
4
3
2
ICIS0 BRSTRM BRSTS1 BRSTS0 —
1
0
1
0
1
R/W
R/W
R/W
R/W
R/W
1
IOS1
1
R/W
0
IOS0
1
R/W
BCR is an 8-bit readable/writable register that specifies the external memory space access mode,
and the extent of the I/O area when the I/O strobe function has been selected for the AS pin.
BCR is initialized to H'D7 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Idle Cycle Insert 1 (ICIS1): Reserved. Do not write 0 to this bit.
Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not a one-state idle cycle is to be inserted
between bus cycles when successive external read and external write cycles are performed.
Bit 6
ICIS0
0
1
Description
Idle cycle not inserted in case of successive external read and external write cycles
Idle cycle inserted in case of successive external read and external write cycles
(Initial value)
Bit 5—Burst ROM Enable (BRSTRM): Selects whether external space is designated as a burst
ROM interface space. The selection applies to the entire external space .
Bit 5
BRSTRM
0
1
Description
Basic bus interface
Burst ROM interface
(Initial value)
Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM
interface.
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