HD64F2149 Datasheet, PDF (889/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

MRB—DTC Mode Register B
H'EC00–H'EFFF
DTC
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
CHNE DISEL —
—
—
—
—
—
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
—
—
—
—
—
—
—
—
DTC interrupt select
0 After a data transfer ends, the CPU interrupt is
disabled unless the transfer counter is 0
1 After a data transfer ends, the CPU interrupt is
enabled
DTC chain transfer enable
0 End of DTC data transfer
1 DTC chain transfer
SAR—DTC Source Address Register
Bit
23 22 21 20 19
Initial value
Read/Write
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
—————
H'EC00–H'EFFF
DTC
---
43210
---
---
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
---
—————
Specifies DTC transfer data source address
DAR—DTC Destination Address Register
Bit
23 22 21 20 19
Initial value
Read/Write
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
—————
H'EC00–H'EFFF
DTC
---
43210
---
---
Unde- Unde- Unde- Unde- Unde-
fined fined fined fined fined
---
—————
Specifies DTC transfer data destination address
855