HD64F2149 Datasheet, PDF (937/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

TCSR—Timer Control/Status Register
H'FF91
FRT
Bit
Initial value
Read/Write
7
ICFA
0
R/(W)*
6
ICFB
0
R/(W)*
5
ICFC
0
R/(W)*
4
ICFD
0
R/(W)*
3
OCFA
0
R/(W)*
2
OCFB
0
R/(W)*
1
OVF
0
R/(W)*
0
CCLRA
0
R/W
Counter clear A
0 FRC clearing is
disabled
1 FRC is cleared at
compare match A
Timer overflow flag
0 [Clearing condition]
Read OVF when OVF = 1,
then write 0 in OVF
1 [Setting condition]
When FRC changes from
H'FFFF to H'0000
Output compare flag B
0 [Clearing condition]
Read OCFB when OCFB = 1, then write 0 in OCFB
1 [Setting condition]
When FRC = OCRB
Output compare flag A
0 [Clearing condition]
Read OCFA when OCFA = 1, then write 0 in OCFA
1 [Setting condition]
When FRC = OCRA
Input capture flag D
0 [Clearing condition]
Read ICFD when ICFD = 1, then write 0 in ICFD
1 [Setting condition]
When an input capture signal is received
Input capture flag C
0 [Clearing condition]
Read ICFC when ICFC = 1, then write 0 in ICFC
1 [Setting condition]
When an input capture signal is received
Input capture flag B
0 [Clearing condition]
Read ICFB when ICFB = 1, then write 0 in ICFB
1 [Setting condition]
When an input capture signal causes the FRC value to be transferred to ICRB
Input capture flag A
0 [Clearing condition]
Read ICFA when ICFA = 1, then write 0 in ICFA
1 [Setting condition]
When an input capture signal causes the FRC value to be transferred to ICRA
Note: * Only 0 can be written in bits 7 to 1, to clear the flags.
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