HD64F2149 Datasheet, PDF (438/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

14.3.4 RESO Signal Output Timing
When TCNT overflows in watchdog timer mode, the OVF bit is set to 1 in TCSR. If the RST/NMI
bit is 1 at this time, an internal reset signal is generated for the entire chip, and at the same time a
low-level signal is output from the RESO pin. The timing is shown in figure 14.6.
ø
TCNT
Overflow signal
(internal signal)
OVF
RESO signal
H'FF
H'00
132 states
Internal reset
signal
518 states
Figure 14.6 RESO Signal Output Timing
14.4 Interrupts
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is selected in
watchdog timer mode, an overflow generates an NMI interrupt request.
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