HD64F2149 Datasheet, PDF (621/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

HICR2 Bit 4—LPC Abort Interrupt Flag (ABRT): Interrupt flag that generates an ERRI
interrupt when a forced termination (abort) of an LPC transfer cycle occurs.
HICR2
Bit 4
ABRT
0
1
Description
[Clearing conditions]
• Writing 0 after reading ABRT = 1
• LPC hardware reset (LRESET pin falling edge detection)
• LPC software reset (LRSTB = 1)
• LPC hardware shutdown
(SDWNE = 1 and LPCPD falling edge detection)
• LPC software shutdown (SDWNB = 1)
(Initial value)
[Setting condition]
• LFRAME pin falling edge detection during LPC transfer cycle
HICR2 Bit 3—IDR3 and TWR receive complete Interrupt Enable (IBFIE3)
HICR2 Bit 2—IDR2 receive complete Interrupt Enable (IBFIE2)
HICR2 Bit 1—IDR1 receive complete Interrupt Enable (IBFIE1)
HICR2 Bit 0—Error Interrupt Enable (ERRIE)
These bits enable or disable IBFI1, IBFI2, IBFI3, and ERRI interrupts to the slave processor.
HICR2
Bit 3
IBFIE3
—
—
—
HICR2
Bit 2
IBFIE2
—
—
—
—
—
—
0
—
1
0
—
1
—
HICR2
Bit 1
IBFIE1
—
—
0
1
—
—
—
—
HICR2
Bit 0
ERRIE
0
1
—
—
—
—
—
—
Description
Error interrupt requests disabled
(Initial value)
Error interrupt requests enabled
Input data register IDR1 receive completed interrupt
request disabled
(Initial value)
Input data register IDR1 receive completed interrupt
request enabled
Input data register IDR2 receive completed interrupt
request disabled
(Initial value)
Input data register IDR2 receive completed interrupt
request enabled
Input data register IDR3 and TWR receive completed
interrupt requests disabled
(Initial value)
Input data register IDR3 and TWR receive completed
interrupt requests enabled
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