HD64F2149 Datasheet, PDF (23/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

9.1 Overview............................................................................................................................ 271
9.1.1 Features ................................................................................................................ 271
9.1.2 Block Diagram...................................................................................................... 272
9.1.3 Pin Configuration ................................................................................................. 273
9.1.4 Register Configuration ......................................................................................... 273
9.2 Register Descriptions......................................................................................................... 274
9.2.1 PWM Register Select (PWSL) ............................................................................. 274
9.2.2 PWM Data Registers (PWDR0 to PWDR15) ...................................................... 276
9.2.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB).................... 276
9.2.4 PWM Output Enable Registers A and B (PWOERA and PWOERB) ................. 277
9.2.5 Peripheral Clock Select Register (PCSR) ............................................................ 278
9.2.6 Port 1 Data Direction Register (P1DDR) ............................................................. 278
9.2.7 Port 2 Data Direction Register (P2DDR) ............................................................. 279
9.2.8 Port 1 Data Register (P1DR) ................................................................................ 279
9.2.9 Port 2 Data Register (P2DR) ................................................................................ 279
9.2.10 Module Stop Control Register (MSTPCR) .......................................................... 280
9.3 Operation ........................................................................................................................... 281
9.3.1 Correspondence between PWM Data Register Contents and Output Waveform 281
Section 10 14-Bit PWM Timer ........................................................................................ 283
10.1 Overview............................................................................................................................ 283
10.1.1 Features ................................................................................................................ 283
10.1.2 Block Diagram...................................................................................................... 284
10.1.3 Pin Configuration ................................................................................................. 284
10.1.4 Register Configuration ......................................................................................... 285
10.2 Register Descriptions......................................................................................................... 285
10.2.1 PWM (D/A) Counter (DACNT) .......................................................................... 285
10.2.2 D/A Data Registers A and B (DADRA and DADRB)......................................... 286
10.2.3 PWM (D/A) Control Register (DACR)................................................................ 287
10.2.4 Module Stop Control Register (MSTPCR) .......................................................... 289
10.3 Bus Master Interface.......................................................................................................... 290
10.4 Operation ........................................................................................................................... 293
Section 11 16-Bit Free-Running Timer ......................................................................... 297
11.1 Overview............................................................................................................................ 297
11.1.1 Features ................................................................................................................ 297
11.1.2 Block Diagram...................................................................................................... 298
11.1.3 Input and Output Pins........................................................................................... 299
11.1.4 Register Configuration ......................................................................................... 300
11.2 Register Descriptions......................................................................................................... 301
11.2.1 Free-Running Counter (FRC)............................................................................... 301
11.2.2 Output Compare Registers A and B (OCRA, OCRB) ......................................... 301
11.2.3 Input Capture Registers A to D (ICRA to ICRD) ................................................ 302
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