HD64F2149 Datasheet, PDF (631/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

SIRQCR0 Bit 4—SMI Interrupt Enable 3B (SMIE3B): Enables or disables a SMI interrupt
request when OBF3B is set by a TWR15 write.
Bit 4
SMIE3B
0
1
Description
SMI interrupt request by OBF3B and SMIE3B is disabled
[Clearing conditions]
• Writing 0 to SMIE3B
• LPC hardware reset, LPC software reset
• Clearing OBF3B to 0 (when IEDIR = 0)
[When IEDIR = 0]
SMI interrupt request by setting OBF3B to 1 is enabled
[When IEDIR = 1]
SMI interrupt is requested
[Setting condition]
• Writing 1 after reading SMIE3B = 0
(Initial value)
SIRQCR0 Bit 3—SMI Interrupt Enable 3A (SMIE3A): Enables or disables a SMI interrupt
request when OBF3A is set by an ODR3 write.
Bit 3
SMIE3A
0
1
Description
SMI interrupt request by OBF3A and SMIE3A is disabled
[Clearing conditions]
• Writing 0 to SMIE3A
• LPC hardware reset, LPC software reset
• Clearing OBF3A to 0 (when IEDIR = 0)
[When IEDIR = 0]
SMI interrupt request by setting OBF3A to 1 is enabled
[When IEDIR = 1]
SMI interrupt is requested
[Setting condition]
• Writing 1 after reading SMIE3A = 0
(Initial value)
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