HD64F2149 Datasheet, PDF (905/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

STR3—Status Register 3
STR4—Status Register 4
Bit
Initial value
Slave R/W
Host R/W
7
DBU
0
R/W
R
6
DBU
0
R/W
R
5
DBU
0
R/W
R
4
DBU
0
R/W
R
H'FE86
H'FE8E
3
2
C/D DBU
0
0
R
R/W
R
R
HIF (XBS)
HIF (XBS)
1
0
IBF OBF
0
0
R R/(W)*
R
R
User-defined bits
Output buffer full
0 [Clearing condition]
When the host processor
reads ODR or the slave
writes 0 in the OBF bit
1 [Setting condition]
When the slave processor
writes to ODR
Input buffer full
0 [Clearing condition]
When the slave processor reads IDR
1 [Setting condition]
When the host processor writes to IDR
Command/data
0 Contents of input data register (IDR) are data
1 Contents of input data register (IDR) are a command
Note: * Only 0 can be written, to clear the flag.
871