HD64F2149 Datasheet, PDF (611/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Name
Abbrevia-
R/W
tion
Slave Host
Initial
Value
Slave
Host
Address*³ Address*⁴
Two-way registers 1 to 15 TWR1 to R/W
TWR15
R/W —
H'FE21 to
H'FE2F
LADR3*⁶
+17/–15
to
LADR3*⁶
+31/–1
SERIRQ control register 0 SIRQCR0 R/W
—
H'00 H'FE36 —
SERIRQ control register 1 SIRQCR1 R/W
—
H'00 H'FE37 —
Module stop control register MSTPCRH R/W
—
H'3F H'FF86 —
MSTPCRL R/W
—
H'FF H'FF87 —
Notes: 1. Bits 5 and 3 are read-only bits.
2. The user-defined bits (channels 1 and 2: bits 7 to 4 and 2; channel 3: bit 2) are
read/write accessible from the slave processor.
3. Address when accessed from the slave processor. The lower 16 bits of the address are
shown.
4. Address when accessed from the host processor.
5. +0 and +4 address calculation is performed, with bit 0 of LADR3 regarded as B'0.
6. +31 to –16 address calculation is performed, with bits 3 to 0 of LADR3 regarded as
B'0000.
18B.2 Register Descriptions
18B.2.1 System Control Registers (SYSCR, SYSCR2)
• SYSCR
Bit
Initial value
Read/Write
7
CS2E
0
R/W
6
5
4
3
2
1
IOSE INTM1 INTM0 XRST NMIEG HIE
0
0
0
1
0
0
R/W
R
R/W
R
R/W
R/W
0
RAME
1
R/W
• SYSCR2
Bit
7
6
5
4
KWUL1 KWUL0 P6PUE
—
Initial value
0
0
0
0
Read/Write
R/W
R/W
R/W
—
3
SDE
0
R/W
2
CS4E
0
R/W
1
CS3E
0
R/W
0
HI12E
0
R/W
577