HD64F2149 Datasheet, PDF (751/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the clock for the bus
master in high-speed mode and medium-speed mode. When operating the device after a transition
to subactive mode or watch mode, bits SCK2 to SCK0 should all be cleared to 0.
Bit 2
SCK2
0
1
Bit 1
SCK1
0
1
0
1
Bit 0
SCK0
0
1
0
1
0
1
—
Description
Bus master is in high-speed mode
Medium-speed clock is ø/2
Medium-speed clock is ø/4
Medium-speed clock is ø/8
Medium-speed clock is ø/16
Medium-speed clock is ø/32
—
(Initial value)
24.2.2 Low-Power Control Register (LPWRCR)
Bit
7
6
5
4
3
2
1
0
DTON LSON NESEL EXCLE —
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
—
—
—
(H8S/2169)
Read/Write R/W
R/W
R/W
R/W
—
—
—
—
(H8S/2149)
LPWRCR is an 8-bit readable/writable register that performs power-down mode control.
LPWRCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Direct-Transfer On Flag (DTON): Specifies whether a direct transition is made between
high-speed mode, medium-speed mode, and subactive mode when making a power-down
transition by executing a SLEEP instruction. The operating mode to which the transition is made
after SLEEP instruction execution is determined by a combination of other control bits.
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