HD64F2149 Datasheet, PDF (96/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 2.6 Effective Address Calculation
Addressing Mode and
No. Instruction Format
1
Register direct (Rn)
Effective Address
Calculation
op rm rn
2
Register indirect (@ERn)
31
0
General register contents
op r
3
Register indirect with displacement
@(d:16, ERn) or @(d:32, ERn)
31
0
General register contents
op r
disp
31
Sign extension
0
disp
Effective Address (EA)
Operand is general register
contents.
31 24 23
0
Don’t
care
31 24 23
0
Don’t
care
4
Register indirect with post-increment or pre-decrement
• Register indirect with post-increment @ERn+
31
0
31 24 23
0
General register contents
Don’t
care
op r
1, 2, or
4
• Register indirect with pre-decrement @–ERn
31
0
op r
General register contents
31 24 23
0
Operand
Size
Byte
Word
Longword
Value
Added
1
2
4
1, 2, or
4
Don’t
care
62