HD64F2149 Datasheet, PDF (597/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR1. Cleared to
0 when the host processor reads ODR.
Bit 0
OBF
0
1
Description
[Clearing condition]
When the host processor reads ODR or the slave writes 0 in the OBF bit (Initial value)
[Setting condition]
When the slave processor writes to ODR
Table 18A.3 shows the conditions for setting and clearing the STR flags.
Table 18A.3 Set/Clear Timing for STR Flags
Flag
Setting Condition
Clearing Condition
C/D
Rising edge of host’s write signal Rising edge of host’s write signal (IOW) when
(IOW) when HA0 is high
HA0 is low
IBF*
Rising edge of host’s write signal
(IOW) when writing to IDR1
Falling edge of slave’s internal read signal (RD)
when reading IDR1
OBF
Falling edge of slave’s internal write Rising edge of host’s read signal (IOR) when
signal (WR) when writing to ODR1 reading ODR1
Note: * The IBF flag setting and clearing conditions are different when the fast A20 gate is used.
For details see table 18A.8, Fast A20 Gate Output Signals.
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