HD64F2149 Datasheet, PDF (25/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

12.3.1 TCNT Incrementation Timing.............................................................................. 347
12.3.2 Compare-Match Timing ....................................................................................... 348
12.3.3 TCNT External Reset Timing .............................................................................. 350
12.3.4 Timing of Overflow Flag (OVF) Setting.............................................................. 350
12.3.5 Operation with Cascaded Connection .................................................................. 351
12.3.6 Input Capture Operation ....................................................................................... 352
12.4 Interrupt Sources................................................................................................................ 354
12.5 8-Bit Timer Application Example ..................................................................................... 355
12.6 Usage Notes ....................................................................................................................... 356
12.6.1 Contention between TCNT Write and Clear........................................................ 356
12.6.2 Contention between TCNT Write and Increment ................................................ 357
12.6.3 Contention between TCOR Write and Compare-Match ...................................... 358
12.6.4 Contention between Compare-Matches A and B ................................................. 359
12.6.5 Switching of Internal Clocks and TCNT Operation............................................. 359
Section 13 Timer Connection ........................................................................................... 363
13.1 Overview............................................................................................................................ 363
13.1.1 Features ................................................................................................................ 363
13.1.2 Block Diagram...................................................................................................... 364
13.1.3 Input and Output Pins........................................................................................... 365
13.1.4 Register Configuration ......................................................................................... 366
13.2 Register Descriptions......................................................................................................... 366
13.2.1 Timer Connection Register I (TCONRI).............................................................. 366
13.2.2 Timer Connection Register O (TCONRO) .......................................................... 369
13.2.3 Timer Connection Register S (TCONRS)............................................................ 371
13.2.4 Edge Sense Register (SEDGR) ............................................................................ 373
13.2.5 Module Stop Control Register (MSTPCR) .......................................................... 375
13.3 Operation ........................................................................................................................... 376
13.3.1 PWM Decoding (PDC Signal Generation) .......................................................... 376
13.3.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) ..................... 378
13.3.3 Measurement of 8-Bit Timer Divided Waveform Period .................................... 379
13.3.4 IHI Signal and 2fH Modification ......................................................................... 381
13.3.5 IVI Signal Fall Modification and IHI Synchronization........................................ 383
13.3.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation) 384
13.3.7 HSYNCO Output.................................................................................................. 387
13.3.8 VSYNCO Output.................................................................................................. 388
13.3.9 CBLANK Output.................................................................................................. 389
Section 14 Watchdog Timer (WDT).............................................................................. 391
14.1 Overview............................................................................................................................ 391
14.1.1 Features ................................................................................................................ 391
14.1.2 Block Diagram...................................................................................................... 392
14.1.3 Pin Configuration ................................................................................................. 393
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