HD64F2149 Datasheet, PDF (646/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Figure 18B.5 shows the timing of the LPCPD and LRESET signals.
LCLK
LPCPD
LAD3–LAD0
LFRAME
LRESET
At least 30 µs
At least 100 µs
At least 60 µs
Figure 18B.5 Power-Down State Termination Timing
18B.3.5 Host Interface Serialized Interrupt Operation (SERIRQ)
A host interrupt request can be issued from the host interface by means of the SERIRQ pin. In a
host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the
serialized interrupt transfer cycle generated by the host or a supporting function, and a request
signal is generated by the frame corresponding to that interrupt. The timing is shown in figure
18B.6.
612