HD64F2149 Datasheet, PDF (596/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

18A.2.6 Status Register (STR)
Bit
7
6
5
4
3
DBU DBU DBU DBU C/D
Initial value
0
0
0
0
0
Slave Read/Write R/W
R/W
R/W
R/W
R
Host Read/Write R
R
R
R
R
2
DBU
0
R/W
R
1
0
IBF
OBF
0
0
R R/(W)*
R
R
Note: * Only 0 can be written, to clear the flag.
STRn (n = 1 to 4) is an 8-bit register that indicates status information during host interface
processing. Bits 3, 1, and 0 are read-only bits to both the host and the slave processors.
STR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 4 and Bit 2—Defined by User (DBU): The user can use these bits as necessary.
Bit 3—Command/Data (C/D): Receives the HA0 input when the host processor writes to IDR,
and indicates whether IDR contains data or a command.
Bit 3
C/D
0
1
Description
Contents of input data register (IDR) are data
Contents of input data register (IDR) are a command
(Initial value)
Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR. This bit is an
internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads
IDR.
The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For
details see table 18A.8, Fast A20 Gate Output Signals.
Bit 1
IBF
0
1
Description
[Clearing condition]
When the slave processor reads IDR
[Setting condition]
When the host processor writes to IDR
(Initial value)
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