HD64F2149 Datasheet, PDF (792/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

ø
RESO
t_RESD
t_RESD
t_RESOW
Figure 25.24 WDT Output Timing (RESO)
Table 25.8 Timing of On-Chip Supporting Modules (2)
Condition: V_CC = 2.7 V to 3.6 V, V_CCB = 2.7 V to 5.5 V, V_SS = 0 V, ø = 2 MHz to maximum
operating frequency, T_a = –20 to +75°C
Condition
10 MHz
Item
Symbol Min
Max
XBS read CS/HA0 setup time
cycle
CS/HA0 hold time
t _HAR
10
—
t _HRA
10
—
IOR pulse width
t _HRPW
220
—
HDB delay time
t _HRD
—
200
HDB hold time
t _HRF
0
40
HIRQ delay time
t _HIRQ
—
200
XBS write CS/HA0 setup time
cycle
CS/HA0 hold time
t _HAW
10
—
t _HWA
10
—
IOW pulse width
t _HWPW
100
—
HDB setup Fast A20 gate not t_HDW
50
—
time
used
Fast A20 gate
used
85
—
HDB hold time
GA20 delay time
t _HWD
25
t _HGA
—
—
180
Unit Test Conditions
ns Figure 25.25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
758