HD64F2149 Datasheet, PDF (929/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

SCR1—Serial Control Register 1
SCR2—Serial Control Register 2
SCR0—Serial Control Register 0
Bit
7
6
5
TIE
RIE
TE
Initial value
0
0
0
Read/Write R/W
R/W
R/W
H'FF8A
H'FFA2
H'FFDA
SCI1
SCI2
SCI0
4
3
2
1
0
RE MPIE TEIE CKE1 CKE0
0
0
0
0
0
R/W R/W R/W R/W R/W
Transmit interrupt enable
0 Transmit-data-empty interrupt
(TXI) request disabled
1 Transmit-data-empty interrupt
(TXI) request enabled
Receive interrupt enable
0 Receive-data-full interrupt (RXI)
request and receive-error interrupt
(ERI) request disabled
1 Receive-data-full interrupt (RXI)
request and receive-error interrupt
(ERI) request enabled
Clock enable 1 and 0
0 0 Asynchronous
mode
Synchronous
mode
1 Asynchronous
mode
Synchronous
mode
1 0 Asynchronous
mode
Synchronous
mode
1 Asynchronous
mode
Synchronous
mode
Internal clock/SCK pin
functions as I/O port
Internal clock/SCK pin
functions as serial clock output
Internal clock/SCK pin
functions as clock output
Internal clock/SCK pin
functions as serial clock output
External clock/SCK pin
functions as clock input
External clock/SCK pin
functions as serial clock input
External clock/SCK pin
functions as clock input
External clock/SCK pin
functions as serial clock input
Transmit end interrupt enable
0 Transmit-end interrupt (TEI) request disabled
1 Transmit-end interrupt (TEI) request enabled
Multiprocessor interrupt enable
0 Multiprocessor interrupts disabled (normal reception mode)
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
1 Multiprocessor interrupts enabled
Receive interrupt (RXI) requests, receive-error interrupt (ERI)
requests, and setting of the RDRF, FER, and ORER flags in
SSR are disabled until data with the multiprocessor bit set to
1 is received
Receive enable
0 Reception disabled
1 Reception enabled
Transmit enable
0 Transmission disabled
1 Transmission enabled
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