HD64F2149 Datasheet, PDF (544/1035 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Master transmit mode
SCL
(Master output)
9
SDA
A
(Slave output)
SDA
(Master output)
IRIC
IRTR
Master receive mode
1
2
3
4
5
6
7
8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 1
[3]
9
1
2
3
4
5
[5]
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Data 2
ICDR
User processing
[1] TRS = 0 clear [2] ICDR read
WAIT = 1 set
(dummy read)
ACKB = 0 clear
[2] IRIC clear
Data 1
[6] ICDR read
(Data 1)
[4] IRIC clear
[7] IRIC clear
Figure 16.8 (1) Example of Master Receive Mode Operating Timing
(MLS = ACKB = 0 and WAIT = 1)
SCL
(Master output)
8
SDA
Bit 0
(Slave output)
Data 2 [8]
SDA
(Master output)
IRIC
IRTR
9
1
2
3
4
5
6
7
8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[5]
Data 3
[8]
A
A
9
1
2
Bit 7 Bit 6
[5]
Data 4
ICDR
User processing
Data 1
[6] ICDR read
(Data 2)
[9] IRIC clear
Data 2
[7] IRIC clear
Data 3
[6] ICDR read
(Data 3)
[9] IRIC clear
[7] IRIC clear
Figure 16.8 (2) Example of Master Receive Mode Operating Timing
(MLS = ACKB = 0 and WAIT = 1)
510